Lucian Petrică

Lecturer, PhD, Faculty of Electronics, Telecommunications and Information Technology,
University Politehnica of Bucharest

Tel: +40723376295
Office: A422, Leu Campus

Last update: June 2013

Research Interests

Degrees and Professional Experience


  • PhD Degree, in Electronics and Telecommunications (Oct 2012), University “Politehnica” of Bucharest.
  • Engineer Degree, in Microelectronics, University “Politehnica” of Bucharest, June 2009.

Academic Activity


All my teaching activity takes place in the Faculty of Electronics, Telecommunications and Information Technology, University “Politehnica” of Bucharest.

Master curricula

  • FPGA Circuit Design, course and applications (2013 – present)
  • Advanced Digital Systems, laboratory (2012 – present)

Bachelor curricula

  • Digital Integrated Circuits, laboratory (2019 – present)
  • Object-Oriented Programming (Java), laboratory (2012 – present);
  • Virtual Instrumentation (LabView), laboratory (2009)

List of publications

PhD thesis

Lucian Petrică, Thread Scheduling for Multithreaded SIMD Processors, PhD Thesis, University “Politehnica” of Bucharest, Oct 2012 (scientific coordinator: prof. Gheorghe Ștefan).

Journal and conference papers


  • Bira, Calin, Liviu Gugu, Radu Hobincu, Lucian Petrică, Valeriu Codreanu, and Sorin Cotofana. “An Energy Effective SIMD Accelerator for Visual Pattern Matching.” In 4th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2013.
  • Petrică, Lucian, Valeriu Codreanu, and Sorin Cotofana. “VASILE: A reconfigurable vector architecture for instruction level frequency scaling.” InFaible Tension Faible Consommation (FTFC), 2013 IEEE, pp. 1-4. IEEE, 2013.


  • Petrica, Lucian. “Dynamic power management through adaptive task scheduling for multi-threaded SIMD processors.” In Electronics and Telecommunications (ISETC), 2012 10th International Symposium on, pp. 83-86. IEEE, 2012.
  • Lucian Petrică, “A SIMD Approach to Thread Matching for Interleaved Multithreading”, In Romanian Journal of Information
    Science and Technology, Volume 15, Number 3, pp. 215–228, 2012.


  • Codreanu, Valeriu, L. Petrica, and Radu Hobincu. “Increasing vector processor pipeline efficiency with a thread-interleaved controller.” In System Theory, Control, and Computing (ICSTCC), 2011 15th International Conference on, pp. 1-4. IEEE, 2011.
  • Hobincu, Radu, Valeriu Codreanu, and Lucian Petrică. “Gnu compiler collection backend port for the integral parallel architecture.” UPB Scientific Bulletin, Series C: Electrical Engineering and Computer Science (2011).


  • Bumbacea, P., Valeriu Codreanu, Radu Hobincu, L. Petrica, and G. M. Stefan. “Technology driven architecture for integral parallel embedded computing.” InSemiconductor Conference (CAS), 2010 International, vol. 1, pp. 35-42. IEEE, 2010.