Course in Bachelor’s program (2nd year, series A, B, F, and G)


Prof. Corneliu Burileanu
Assoc. Prof. Horia Cucu

Lect. Georgian Nicolae
Dr. Ana Neacșu
Lect. George-Vlăduț Popescu
Dr. Diana Grosu-Șandru
As. Andrei Dăescu

Course Description

Introducing several typical microcontroller architectures: 8051 core, “Arduino” Systems and ARM family. Study of the advanced principles in CISC and RISC microprocessor architecture: memory management, protected mode, multitasking, CISC and RISC architecture convergence in actual processors. In the laboratory-type applications, the students are guided in developing practical applications for the C8051F040 microcontroller.



  • “Memory Management” – Virtual Memory, Virtual Memory Segmentation, Paging Mechanism
  • “Protection Methods” – Types of Protection, Memory Management and Protection, Multi-Level Privileges and Protection, Data and Programs Protection, Control Transfer between Protection Levels, Page Protection, Interrupts and Exceptions in Virtual (Protected) Mode
  • “Multitasking” – Definitions, Task State Segment and the Related Descriptor, Task switching, Task Gate
  • “8051 Microcontroller Core” – General Features, Memory Organization, Register Set, Addressing Techniques, Instruction Set, Instruction Timing
  • “Arduino Systems” – Arduino Uno, ATmega48A/PA/88A/PA/168A/PA/328/P, AVR CPU Core, GALILEO Board, Programming Examples
  • “ARM Architecture Microcontrollers” – General Features, Processor Modes, Register Set, Memory and Port Organization, Instruction Set, Programming Examples


  • An integrated development tool for 8051 core microcontrollers (IDE – “Integrated Development Environment”)
  • Overall view on Silicon Labs – C8051F040 “System on a Chip”
  • Application using the analog to digital converter
  • Application using the UART system
  • Application using the digital to analog converter
  • Application using the interrupts system
  • Laboratory assessment

Additional resources

C8051F04x MCUs 8-bit
Silicon Laboratories IDE


Laboratory evaluation (multiple verification tests + optional oral evaluation): 50%
Course final exam (verification quiz + optional written and oral evaluation): 50%